1. Field of the Invention
The invention relates to a semiconductor memory device, and more particularly to the improvement of a reference section which generates a reference current for use in identification of data in a memory cell selected.
2. Description of the Related Art
In some methods for reading data from a semiconductor memory device, an electric current ISA flowing through a memory cell and a reference current IRA are compared with each other to make 0/1 identification of data. These methods are widely used, for example, in read only memories and the like having flat type memory cells.
For easy understanding of the subsequent description, an explanation will here be made on the general configuration of a typical read only semiconductor memory chip using flat type memory cells to which the present invention is applicable.
FIG. 1 is a plan view showing the general configuration of a semiconductor memory chip using flat type memory cells. FIGS. 2A and 2B are plan views showing the general configuration of a unit memory cell block constituting a memory cell array section in the semiconductor memory device and an example of the arrangement thereof, respectively. FIG. 3 is a plan view schematically showing the positional relation between a metal wiring, serving as a bit line or a virtual ground line, and diffusion regions for contact in a memory cell array section.
Moreover, FIG. 4 is a schematic plan view showing the arrangement of the contact diffusion regions in each reference cell block constituting a conventional reference section of the semiconductor memory device, in a simplified form for the sake of clarity. FIG. 5 is a schematic plan view showing an example of the general configuration of this reference section, along with a part of a memory cell array section.
First, referring to FIGS. 1-3, a memory chip 1 of the semiconductor memory device using flat type memory cells comprises memory cell array sections 2, reference sections 3, decoder sections 4, peripheral circuit sections 5, and the like.
To improve the degree of integration, the memory cell array sections 2 are usually composed of memory cell blocks 10 arranged as shown in FIG. 2B. In the vertical direction, the memory cell blocks 10 are arranged to be symmetric to one another about the border lines thereof, and more specifically, so that they make vertical turns at the respective centers of first contact diffusion regions 13 and second contact diffusion regions 14 in FIG. 2A. In the horizontal direction, the memory cell blocks 10 are arranged parallel to one another.
Each of the memory cell blocks 10 includes a memory cell part 11, block selector parts 12 and 19, and the first and second contact diffusion regions 13 and 14 for establishing connection with a bit line 17 and a virtual ground line 18. Besides, the memory cell part 11 and the block selector parts 12, 19 include a plurality of diffusion layers 20, word lines 21a, and block selecting signal lines 22a. The diffusion layers 20 are arranged parallel to one another. The word lines 21a and the block selecting signal lines 22a are orthogonal to the diffusion layers 20.
As mentioned above, the memory cell array sections 2 comprise the memory cell blocks 10 which are arranged to make turns at the respective centers of the first contact diffusion regions 13 (13a-13d, in FIG. 3) and the second contact diffusion regions 14 (14a-14d, in FIG. 3). With respect to each bit line 17, 17a and each virtual ground line 18, 18a, the first contact diffusion regions 13, 13a-13d and the second contact diffusion regions 14, 14a-14d, along with the contact holes 15, 15a-15d and the contact holes 16, 16a-16d, are arranged in the proportions of ones to two memory cell blocks 10, thereby establishing connection with the bit line 17, 17a and the virtual ground line 18, 18a, respectively.
Now, referring to FIGS. 4 and 5, a conventional reference section 30 in this semiconductor memory device comprises reference cell blocks 31 having the same configuration as that of the memory cell blocks 10. The reference cell blocks 31 are also arranged to make vertical turns at the respective centers of first contact diffusion regions 32a-32d and second contact diffusion regions 33a-33d. The contact diffusion regions at required positions, e.g. the first contact diffusion region 32b and the second contact diffusion region 33d in FIG. 4, are provided with contact holes 34 and 35 to establish connection with a bit line 27 and a virtual ground line 28, respectively.
FIG. 6 is a schematic circuit diagram for explaining the methods of selecting and reading a memory cell in the reference cell when reading data from a memory cell in the semiconductor memory device described above.
Referring to FIG. 6, upon data read from a flat type memory cell 611a, the value of a current ISA and the value of a current IRA are compared with each other so that their magnitudes are judged by a sense amplifier 600 to make 0/1 identification of the data stored in the memory cell 611a. Here, ISA is a current that flows through a first contact diffusion region 613a, the memory cell 611a, and a second contact diffusion region 614a to a virtual ground line when a bit line drive circuit 601 gives a potential to the bit line to select the memory cell 611a. IRA is a current that flows through a first contact diffusion region 632a, a memory cell transistor 671a, a second contact diffusion region 633a, a memory cell transistor 617b, a first contact diffusion region 632b, a memory cell transistor 617c, and a second contact diffusion region 633b to a virtual ground line when a bit line drive circuit 602 gives a potential to the bit line in the reference section.
The memory cell transistors, however, vary in ON current value ISO because of fluctuations in manufacture conditions and the like. Accordingly, IRA is usually set to 1/k of ISO (where k is an integer not smaller than xe2x80x9c2xe2x80x9d) for surer data identification.
In this example, the three reference cell blocks 631a-631c are connected in series to set the reference current value IRA to ⅓ the ON current value ISO of the memory cell transistors.
In recent years, finer processes have increased variations in device characteristics (a drop in ON current, a rise in OFF current (leak current), and the like) even within an identical chip. Accordingly, there has been an increasing need for the finer settings of the reference current value IRA so as to improve the accuracy of the data identification in memory cells.
Nevertheless, the conventional reference section 30 is constituted so that the reference cell blocks 31 having the same configuration as that of the memory cell blocks 10 make turns at the centers of the respective contact diffusion regions as in the memory cell array sections 2. Therefore, the bit line 27 or the virtual ground line 28, consisting of metal wiring, and the first and second contact diffusion regions 32a-32d, 33a-33d come into such physical relation as shown in FIG. 4.
In general, connecting a plurality of reference cell blocks 31 in series requires that a current path also run from a first contact diffusion region 32a-32d through the reference cell blocks 31 and reach a virtual ground line 28 via a second contact diffusion region 33a-33d. Thus, the positions to connect the bit line 27 and the virtual ground line 28 with the first contact diffusion region 32a-32d and the second contact diffusion region 33a-33d, respectively, determine the number of blocks in the serial connection.
Since the first contact diffusion regions and the second contact diffusion regions are arranged alternately in the proportions of ones to two reference cell blocks 31 as shown in FIG. 4, the reference cell blocks 31 connected in series cannot usually realize a serial connection of even number.
This has brought about the problem that the reference current value IRA can only be set to 1/(2mxe2x88x921) of ISO (where m is an integer not less than xe2x80x9c1xe2x80x9d), hampering finer settings of the reference current value IRA.
An object of the present invention is to provide a semiconductor memory device whose reference sections are devised in pattern configuration so that the number of reference cell blocks to be connected in series is not limited to odd numbers and can be set freely, thereby allowing finer settings of the reference current value.
A semiconductor memory device according to the present invention comprises a memory cell array section having a plurality of memory cell blocks arranged in a matrix, the memory cell blocks each including a plurality of memory cells; and a reference section for generating a reference current for use in identification of data stored in the memory cells. The reference section includes: a plurality of diffusion layers arranged parallel to each other; a plurality of word lines arranged parallel to each other along a direction orthogonal to the diffusion layers; a plurality of MOS transistors having sources and drains made of the intersections of the diffusion layers and the word lines, and channels made of the portions sandwiched between the sources and drains; and first contact diffusion regions and second contact diffusion regions for connecting the diffusion layers with a bit line and a virtual ground line. All the second contact diffusion regions are provided with a contact to the virtual ground line.
The reference section may include a plurality of unit reference cell blocks each having the same size in a bit-line direction as that of the memory cell blocks. Here, the array pitch and the number of the reference cell blocks in the reference section are the same as the array pitch and the number in the bit-line direction of the memory cell blocks in the memory cell array section. Each of the reference cell blocks includes: a plurality of diffusion layers arranged parallel to each other; a plurality of word lines arranged parallel to each other along a direction orthogonal to the diffusion layers; a plurality of MOS transistors having sources and drains made of the intersections of the diffusion layers and the word lines, and channels made of the portions sandwiched between the sources and drains; a first contact diffusion region and a second contact diffusion region for connecting the diffusion layers with a bit line and a virtual ground line, respectively; a plurality of block selecting signal lines arranged between the word lines and at least either one of the first contact diffusion region and the second contact diffusion region so as to be parallel to the word lines; and block selecting transistors having sources and drains made of the intersections of the plurality of diffusion layers and the block selecting signal lines. All the second contact diffusion regions formed under the virtual ground line are provided with a contact to the virtual ground line.
Each of the memory cell blocks may also include: a plurality of diffusion layers arranged parallel to each other; a first contact diffusion region and a second contact diffusion region for connecting the diffusion layers with a bit line and a virtual ground line, respectively; a plurality of word lines arranged between the first contact diffusion region and the second contact diffusion region so as to be parallel to each other along a direction orthogonal to the diffusion layers; a plurality of memory cells having sources and drains made of the intersections of the diffusion layers and the word lines, and channels made of the portions sandwiched between the sources and drains; a plurality of block selecting signal lines arranged between the word lines and the first contact diffusion region as well as the second contact diffusion regions, so as to be parallel to the word lines; and block selecting transistors having sources and drains made of the intersections of the plurality of diffusion layers and the block selecting signal lines.
Here, the word lines, the diffusion layers, and the block selecting signal lines in the reference cell blocks and the memory cell blocks are preferably identical to each other in array pitch and in width.
Moreover, any of the reference cell blocks, when generating the reference current, activates no more than one MOS transistor among the plurality of MOS transistors made of the word lines and the diffusion layers in the reference cell block.
Furthermore, another semiconductor memory device according to the present invention comprises memory cell blocks and reference cell blocks. Each of the blocks includes: a plurality of diffusion layers arranged parallel to each other; a first contact diffusion region and a second contact diffusion region formed under a bit line and a virtual ground line, for connecting the diffusion layers with the bit line and the virtual ground line, respectively; a plurality of word lines arranged between the first contact diffusion region and the second contact diffusion region, so as to be parallel to each other along a direction orthogonal to the diffusion layers; a plurality of memory cells having sources and drains made of the intersections of the diffusion layers and the word lines, and channels made of the portions sandwiched between the sources and drains; a plurality of block selecting signal lines arranged between the word lines and the first contact diffusion region as well as the second contact diffusion region so as to be parallel to the word lines; and block selecting transistors having sources and drains made of the intersections of the plurality of diffusion layers and the block selecting signal lines. All those second contact diffusion regions of the reference cell blocks, not connected to the virtual ground line are shifted in parallel with the word lines to under the bit line to form third contact diffusion regions.
The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals.